1. Field of the Invention
The invention relates to the field of computers, and more particularly to processors executing machine coded instructions which specify operands.
2. Description of the Relevant Art
The vast amount of software developed for 80xc3x9786 (x86) processors (i.e., 8086/8, 80286, 80386, 80486, and Pentium processors) makes it highly advantageous for processor manufacturers to produce products which execute x86 instructions, thereby maintaining xe2x80x9cbackwards compatabilityxe2x80x9d with existing x86 software. Maintaining software compatibility is often achieved by simply modifying or extending existing hardware in order to add new features and/or increase performance.
The x86 instruction set is relatively complex and is characterized by variable byte length instructions. FIG. 1 is a diagram of a generic x86 instruction 10. As shown in FIG. 1, x86 instruction 10 includes an optional prefix field 12, an operation code (opcode) field 14, an optional addressing mode (MODR/M) byte 16, an optional scale-index-base (SIB) byte 18, an optional displacement field 20, and an optional immediate field 22. Optional prefix field 12 includes one to five 8-bit prefix bytes. Opcode field 14 follows prefix field 12, and includes one or two opcode bytes. Opcode field 14 defines the operation performed by instruction 10. Prefix bytes within prefix field 12 may modify the operation of instruction 10 defined by opcode field 14. For example, a prefix byte within prefix field 12 may change the address or operand size for instruction 10, override the default segment used in memory addressing, or instruct the processor to repeat a string operation a number of times.
Optional MODR/M byte 16 follows opcode field 14, and includes information specifying operand types, registers used during execution of instruction 10, and memory addressing modes. FIG. 2 is a diagram of optional MODR/M byte 16 of x86 instruction of FIG. 1. Optional MODR/M byte 16 includes a mode (MOD) field 24, a register/operation (REG/OP) field 26, and a register/memory (R/M) field 28. MOD field 24 includes bits 7 and 6 of MODR/M byte 16. The two bits of MOD field 24 determine how RIM field 28 and optional displacement field 20 are interpreted. REG/OP field 26 includes bits 5, 4, and 3 of MODR/M byte 16. The three bits of REG/OP field 26 are used either to: (i) specify a register operand, or (ii) hold additional bits of opcode field 14. R/M field 28 includes bits 2, 1, and 0 of MODR/M byte 16. The three bits of R/M field 28 specify either a register source operand (MOD=xe2x80x9811xe2x80x99) or a memory reference (MOD xe2x89xa0xe2x80x9811xe2x80x99).
Optional SIB byte 18 follows optional MODR/M byte 16, and is used only in 32-bit base-relative addressing using scale and index factors. FIG SIB byte 18 of x86 instruction 10 of FIG. 1. SIB byte 18 includes a scale field 30, an index field 32, and a base field 34. Base field 34 includes bits 2-0 of SIB byte 18, and specifies which register contains the base value for the address calculation. Index field 32 includes bits 5-3 of SIB byte 18, and specifies which register contains the index value. Scale field 30 includes bits 7-6 of SIB byte 18, and specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value.
Optional displacement field 20 follows SIB byte 18, and includes one to four bytes of displacement data. The displacement data forms a constant used in address calculations. Optional immediate field 22 follows optional displacement field 20, and includes one to four bytes of a constant used as an instruction operand.
Each instruction of the x86 instruction set defines an operation carried out using 0, 1, or 2 operands. For example, a first subset of the x86 instruction set includes instructions consisting of a single opcode byte and having no operands (e.g., NOP and HLT). A second subset of the x86 instruction set includes instructions having a single operand which functions as both a source operand and a destination operand (e.g., INC and DEC). The single operand may be a value stored in a register or a memory location. When the single operand is a register value, the register is specified by the encoding of the 3 least significant bits of a single opcode byte within opcode field 14. When the single operand is a value stored within a memory location, the memory location is specified by values encoded within MODR/M byte 16 and displacement data within displacement field 20.
A third subset of the x86 instruction set includes instructions having two operands: a source operand and a destination operand (e.g., ADD and SUB). The source and destination operands are involved in the operation, and a result of the operation is stored in the destination operand and used to set flag bits within a flag register. The source and destination operands may be registers or memory locations specified by the encoding of the opcode byte within opcode field 14, values encoded within MODR/M byte 16, and displacement data within displacement field 20. Alternately, the source operand may be a constant value specified by immediate data within immediate field 22.
FIG. 4 is a diagram of an exemplary last opcode byte 36 within opcode field 14 of x86 instruction 10 of FIG. 1. Bit 1 of last opcode byte 36 may be a direction (D) bit or a sign (S) bit. The direction bit determines whether the register specified in REG/OP field 26 of MODR/M field 16 is a source operand or a destination operand of x86 instruction 10. If D=0, REG/OP field 26 specifies a register which is the source operand. On the other hand, if D=1, the destination operand is a register specified by REG/OP field 26, and the source operand may be a memory operand or another register operand. When bit 1 of last opcode byte 36 is a sign bit and S=1, the immediate data within immediate field 22 is sign extended to full operand length before use. If S=0, the immediate data is not modified. It is noted that the direction and/or sign bits may be located at any bit positions within any opcode byte of x86 instruction 10.
Bit 0 of last opcode byte 36 may be a width (W) bit. The width bit determines whether the operands are treated as 8-bit, 16-bit, or 32-bit quantities. If W=0, both the source and destination operands are treated as 8-bit quantities. If W=1, operand size is determined by the current operating mode of the processor. For example, if the processor is operating in a 16-bit mode and W=1, both operands will be treated as 16-bit quantities. On the other hand, if the processor is operating in a 32-bit mode and W=1, both operands will be treated as 32-bit quantities. In accordance with the above, REG/OP field 26 of MODR/M field 16 specifies either an 8-bit, a 16-bit, or a 32-bit register dependent upon the value of the width bit and the current operating mode of the processor. It is noted that the width bit may be located at any bit position within any opcode byte of x86 instruction 10.
A typical processor includes an instruction decoder which receives and decodes instructions, to include operand information, and a xe2x80x9cfunctional unitxe2x80x9d which receives the decoded instructions and operand information from the instruction decoder and executes the decoded instructions. In order to produce a result which corresponds to a destination operand, the functional unit may require that a source operand always be provided at one input and the destination operand always be provided at another input. As the source operand may be specified before or after the destination operand within x86 instructions, the decoder may require additional hardware to reorder the source and destination operands if necessary before providing the operands to the functional unit.
It would thus be advantageous to have an instruction decoder which produces operand information in the order in which the operands are identified within the instruction. Such an instruction decoder would eliminate any need for additional hardware to reorder source and destination operands delivered to the functional unit.
An instruction decode unit is described including circuitry coupled to receive an instruction. The instruction identifies multiple operands, one of which is a destination operand. The circuitry responds to the instruction by producing: (i) operand codes specifying the operands, wherein the operand codes are produced in the order in which the operands are identified within the instruction, and (ii) a destination operand signal identifying the destination operand. In one embodiment, the decode unit responds to the instruction by producing the operand codes, operand address information, control signals, and the destination operand signal. A processor including the instruction decode unit is also described, as is a computer system including the processor.
The instruction may include operand information which identifies the operands. The instruction may also include destination operand information which indicates which of the operands is the destination operand. The circuitry may produce the destination operand signal dependent upon the destination operand information. The instruction may be a member of an instruction set including instructions having a variable number of bytes. In one particular example, the instruction may be an x86 instruction including operand information which identifies two operands. The instruction may include a direction bit, and the value of the direction bit may indicate which of the two operands is the destination operand. In this case, the circuitry may produce the destination operand signal dependent upon the value of the direction bit.
In addition to the decode unit, the processor may include a reservation station, a functional unit, and a reorder buffer. The reservation station, the functional unit, and the reorder buffer may be coupled to a result bus. The decode unit may provide the operand codes and the destination operand signal to the reorder buffer. In response to the operand codes, the reorder buffer may produce either operand values or tags associated with the operand values. The reorder buffer may also produce a result tag associated with the instruction. If the destination operand is a register, the result tag may be associated with a storage location within the reorder buffer and reserved for the result. If the destination operand is a memory location, the reorder buffer may forward a copy of the result tag to a load/store unit coupled to the result bus and a memory.
The reservation station may receive and store the operand values/tags and the result tag from the reorder buffer, and the operand address information, the control signals, and the destination operand signal from the decode unit. The reservation station may continuously monitor the result bus. If a tag driven upon the result bus matches an operand tag stored within the reservation station, the reservation station may replace the operand tag with the corresponding value driven upon the result bus. The reservation station may dispatch operands, control signals, the result tag, and the destination operand signal of a given instruction to the functional unit only when all operand tags associated with the instruction have been replaced with operand values.
The functional unit may receive the operand values, control signals, the result tag, and the destination operand signal from the reservation station. The functional unit may perform an arithmetic/logic operation using the operands and dependent upon the control signals and the destination operand signal. The functional unit may produce a result via the arithmetic/logic operation, and may drive the result value and the result tag upon the result bus.
When one of the operands is a memory operand, the functional unit may receive the operand address information, the control signals, and the operand tag from the reservation station. The functional unit may perform an address calculation upon the operand address information dependent upon the control signals, and provide the resulting address information and operand tag to the load/store unit.
The computer system may include the above processor, a bus coupled to the processor, and a peripheral device coupled to the bus. The bus may be a peripheral component interconnect (PCI) bus, and the peripheral device may be, for example, a network interface card, a video accelerator, an audio card, a hard disk drive, or a floppy disk drive. Alternately, the bus may be an extended industry standard architecture (EISA)/industry standard architecture (ISA) bus, and the peripheral device may be, for example, a modem, a sound card, or a data acquisition card.